Developer CD Series 1999 October: Technology Seed

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/ Developer CD Series 1999 October: Technology Seed / ADC Seed CD - October 1999.toast / FireWire / FireWire_2.1_SDK_DR3 / Source / FWIM / PeleFWIM / PeleFWIM.h < prev next >

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C/C++ Source or Header | 1999-05-17 | 37.0 KB | 1,164 lines | [TEXT/MPS ]

/* File: PeleFWIM.h Contains: Definitions for Pele 1394 card FireWire interface module. Written by: Eric W. Anderson Copyright: © 1997 by Apple Computer, Inc., all rights reserved. Change History (most recent first): <FW2> 6/5/96 EA Fill in contains and written by fields. <FW1> 6/5/96 EA first checked in */ #ifndef __PELEFWIM__ #define __PELEFWIM__ #ifndef __TYPES__ #include <Types.h> #endif #ifndef __INTERRUPTS__ #include <Interrupts.h> #endif #ifdef __cplusplus extern "C" { #endif #if PRAGMA_IMPORT_SUPPORTED #pragma import on #endif #if PRAGMA_ALIGN_SUPPORTED #pragma options align=power #endif /*zzz*/ /* Isn't this PCI standard stuff? Shouldn't it be in some regular include */ /* file like PCI.h? */ #define bit0 0x00000001 #define bit1 0x00000002 #define bit2 0x00000004 #define bit3 0x00000008 #define bit4 0x00000010 #define bit5 0x00000020 #define bit6 0x00000040 #define bit7 0x00000080 #define bit8 0x00000100 #define bit9 0x00000200 #define bit10 0x00000400 #define bit11 0x00000800 #define bit12 0x00001000 #define bit13 0x00002000 #define bit14 0x00004000 #define bit15 0x00008000 #define bit16 0x00010000 #define bit17 0x00020000 #define bit18 0x00040000 #define bit19 0x00080000 #define bit20 0x00100000 #define bit21 0x00200000 #define bit22 0x00400000 #define bit23 0x00800000 #define bit24 0x01000000 #define bit25 0x02000000 #define bit26 0x04000000 #define bit27 0x08000000 #define bit28 0x10000000 #define bit29 0x20000000 #define bit30 0x40000000 #define bit31 0x80000000 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Configuration Registers * */ enum { kConfigStart = 0x00, cwVendorID = 0x00, /* 0x1000 */ cwDeviceID = 0x02, /* 0x0003 */ cwCommand = 0x04, cwStatus = 0x06, clClassCodeAndRevID = 0x08, clHeaderAndLatency = 0x0C, clBaseAddressZero = 0x10, /* I/O Base address */ clBaseAddressOne = 0x14, /* Memory Base address */ clExpansionRomAddr = 0x30, clLatGntIntPinLine = 0x3C, /* Max_Lat, Max_Gnt, Int. Pin, Int. Line */ kConfigEnd = 0x40 }; /* * 0x04 cwCommand Command Register (read/write) */ enum { cwCommandSERREnable = bit8, cwCommandEnableParityError = bit6, cwCommandEnableBusMaster = bit2, /* Set this on initialization */ cwCommandEnableMemorySpace = bit1, /* Respond at Base Address One if set */ cwCommandEnableIOSpace = bit0 /* Respond at Base Address Zero if set */ }; /* * 0x06 cwStatus Status Register (read/write) */ enum { cwStatusDetectedParityError = bit15, /* Detected from slave */ cwStatusSignaledSystemError = bit14, /* Device asserts SERR/ signal */ cwStatusMasterAbort = bit13, /* Master sets when transaction aborts */ cwStatusReceivedTargetAbort = bit12, /* Master sets when target-abort */ cwStatusDEVSELTimingMask = (bit10 | bit9), /* DEVSEL timing encoding R/O */ cwStatusDEVSELFastTiming = 0, cwStatusDEVSELMediumTiming = bit9, cwStatusDEVSELSlowTiming = bit10, cwStatusDataParityReported = bit8 }; /*zzz*/ //////////////////////////////////////////////////////////////////////////////// // // Useful macro def. // This is useful for swapping constants (compiler will simplify). // This may be faster for swapping variables. // Do not use on expressions with side effects (e.g. function calls) // #define EndianSwapImm32Bit(data32) \ ( \ (((UInt32) data32) >> 24) | \ ((((UInt32) data32) >> 8) & 0xFF00) | \ ((((UInt32) data32) << 8) & 0xFF0000) | \ (((UInt32) data32) << 24) \ ) //////////////////////////////////////////////////////////////////////////////// // // FWIM data defs. // enum { // kAsynchDMA = 0, // Channels we chose... // Need to clean up a little, these are Lynx numbers: kIsochReceiveDMA = 2, // kIsochTransmitDMA = 3, // // kTransmitDMA = 4, // Lowest priority (would rather receive) // Used in PeleFWIM.h, clean up kNumDMAChannels = 5, // Number of DMA channels. // Use these intead kPeleDMAAsynchTx = 0, // Channel numbers from Table 3-2 kPeleDMAAsynchRx = 1, // Used for callProc interrupts, etc. kPeleDMAIsochTxA = 2, kPeleDMAIsochTxB = 3, kPeleDMAIsochRxA = 4, kPeleDMAIsochRxB = 5, kPeleDMACount = 6, // About 192K could be saved by packing three ~1040-byte receive buffers to a page. // Another 170K or so could by saved if all async buffers were contiguous. kAsyncRxPacketBufferSize = 2048, // Largest legal asynch packet is 1040 // bytes (200 mb) // kAsyncRxPacketBufferSize must be multiple of 32 kMaxBufPage = 8, // Max # of physical pages per packet kAsynchTxDoneDMA = 0, // Asynch transmit done DMA index. kAsynchTxDataDMA = 2, // Asynch transmit data DMA index. kNumAsynchTxDMAs = 16, // Number of DMAs for asynch transmit. kAsynchRxOverrunDMA = 0, // Asynch receive overrun DMA index. kAsynchRxFirstPacketDMA = 3, // First asynch receive packet DMA index. kAsynchRxLastPacketDMA = 255, // Last asynch receive packet DMA index. kAsynchRxBufs = 256, // # of Asynch bufs kPeleNumAsynchRxDMAsToPrime = 20, // kIsochTransmitPort = 1, // Transmitting isoch port number. // kIsochReceivePort = 2 // Receiving isoch port number. }; // Strictly speaking, the "Pele PHY" is the TI TSB21LV03 200 megabit PHY. // If Pele is used with another PHY, these constants may (or may not) change. // These are all the same as the old TI TSB11C01DL PHY from the TI P1394 card. //////////////////////////////////////////////////////////////////////////////// // // Phy registers. // enum { kPelePhyBit0 = (1 << 7), kPelePhyBit1 = (1 << 6), kPelePhyBit2 = (1 << 5), kPelePhyBit3 = (1 << 4), kPelePhyBit4 = (1 << 3), kPelePhyBit5 = (1 << 2), kPelePhyBit6 = (1 << 1), kPelePhyBit7 = (1 << 0) }; #define PelePhyBitRange(start, end) \ ( \ (((((UInt32) 0xFF) << (start)) & 0xFF) >> \ ((start) + (7 - (end)))) << \ (7 - (end)) \ ) #define PelePhyBitRangePhase(start, end) \ (7 - end) // Phy register defs, as per 1394-1995 enum { kPelePhyPhysicalIDAddress = 0, kPelePhyPhysicalID = PelePhyBitRange (0, 5), kPelePhyPhysicalIDPhase = PelePhyBitRangePhase (0, 5), kPelePhyRAddress = 0, kPelePhyR = kPelePhyBit6, kPelePhyCPSAddress = 0, kPelePhyCPS = kPelePhyBit7, kPelePhyRHBAddress = 1, kPelePhyRHB = kPelePhyBit0, kPelePhyIBRAddress = 1, kPelePhyIBR = kPelePhyBit1, kPelePhyGCAddress = 1, kPelePhyGC = PelePhyBitRange (2, 7), kPelePhyGCPhase = PelePhyBitRangePhase (2, 7), kPelePhySPDAddress = 2, kPelePhySPD = PelePhyBitRange (0, 1), kPelePhySPDPhase = PelePhyBitRangePhase (0, 1), kPelePhyNPAddress = 2, kPelePhyNP = PelePhyBitRange (3, 7), kPelePhyNPPhase = PelePhyBitRangePhase (3, 7), kPelePhyAStat1Address = 3, kPelePhyAStat1 = PelePhyBitRange (0, 1), kPelePhyAStat1Phase = PelePhyBitRangePhase (0, 1), kPelePhyBStat1Address = 3, kPelePhyBStat1 = PelePhyBitRange (2, 3), kPelePhyBStat1Phase = PelePhyBitRangePhase (2, 3), kPelePhyPortStatus1Address = 3, kPelePhyPortStatus1 = PelePhyBitRange (4, 5), kPelePhyPortStatus1Phase = PelePhyBitRangePhase (4, 5), kPelePhyCh1Address = 3, kPelePhyCh1 = kPelePhyBit4, kPelePhyCon1Address = 3, kPelePhyCon1 = kPelePhyBit5, kPelePhyAStat2Address = 4, kPelePhyAStat2 = PelePhyBitRange (0, 1), kPelePhyAStat2Phase = PelePhyBitRangePhase (0, 1), kPelePhyBStat2Address = 4, kPelePhyBStat2 = PelePhyBitRange (2, 3), kPelePhyBStat2Phase = PelePhyBitRangePhase (2, 3), kPelePhyPortStatus2Address = 4, kPelePhyPortStatus2 = PelePhyBitRange (4, 5), kPelePhyPortStatus2Phase = PelePhyBitRangePhase (4, 5), kPelePhyCh2Address = 4, kPelePhyCh2 = kPelePhyBit4, kPelePhyCon2Address = 4, kPelePhyCon2 = kPelePhyBit5, kPelePhyAStat3Address = 5, kPelePhyAStat3 = PelePhyBitRange (0, 1), kPelePhyAStat3Phase = PelePhyBitRangePhase (0, 1), kPelePhyBStat3Address = 5, kPelePhyBStat3 = PelePhyBitRange (2, 3), kPelePhyBStat3Phase = PelePhyBitRangePhase (2, 3), kPelePhyPortStatus3Address = 5, kPelePhyPortStatus3 = PelePhyBitRange (4, 5), kPelePhyPortStatus3Phase = PelePhyBitRangePhase (4, 5), kPelePhyCh3Address = 5, kPelePhyCh3 = kPelePhyBit4, kPelePhyCon3Address = 5, kPelePhyCon3 = kPelePhyBit5, kPelePhyCAddress = 6, kPelePhyC = kPelePhyBit7, kPelePhyInvalidAddress = 15 }; //////////////////////////////////////////////////////////////////////////////// // // Pele registers. Based on the 0.93v0 spec // // This struct matches struct DBDMAChannelRegisters from DBDMA.h, except that // the Pele one is cut short (just 32 bytes). There is one of these for each // of the 6 DMA channels (Asynch xmit/rcv, Iso xmit A/B, Iso rcv A/B). Also, // except for Asynch transmit, the Select registers aren't implemented in Pele. struct PeleDBDMAChannelRegistersStruct { volatile UInt32 channelControl; volatile UInt32 channelStatus; volatile UInt32 reserved8; volatile UInt32 commandPtr; volatile UInt32 interruptSelect; // Asynch xmit only volatile UInt32 branchSelect; // Asynch xmit only volatile UInt32 waitSelect; // Asynch xmit only volatile UInt32 reserved1C; }; typedef struct PeleDBDMAChannelRegistersStruct PeleDBDMAChannelRegisters, *PeleDBDMAChannelRegistersPtr; // This is Pele-specific, and controls Isoch functions (like start-on-cycle). // The bandwidthControl is transmit only. // There are four of these, one each for Iso xmit A/B and rcv A/B. struct PeleIsochControlRegistersStruct { volatile UInt32 eventCycle; volatile UInt32 configuration; volatile UInt32 bandwidthControl; // Xmit only volatile UInt32 reservedC; }; typedef struct PeleIsochControlRegistersStruct PeleIsochControlRegisters, *PeleIsochControlRegistersPtr; // This is not a register; this is the DBDMA command program element. // String these together in main memory and give Pele the address to run from. struct PeleDBDMADescriptor { unsigned long operation; unsigned long address; unsigned long cmdDep; unsigned long result; }; typedef struct PeleDBDMADescriptor PeleDBDMADescriptor, PeleDMA, // shorthand *PeleDBDMADescriptorPtr, *PeleDMAPtr; // shorthand // This is the main Pele register file, 512 bytes long. Note that unlike // some other 1394 chips, the PCI control registers aren't included here. struct PeleRegistersStruct { PeleDBDMAChannelRegisters asynchTransmit; PeleDBDMAChannelRegisters asynchReceive; PeleDBDMAChannelRegisters isochTransmitA; PeleDBDMAChannelRegisters isochTransmitB; PeleDBDMAChannelRegisters isochReceiveA; PeleDBDMAChannelRegisters isochReceiveB; volatile UInt32 reservedC0[16]; volatile UInt32 version; volatile UInt32 control; volatile UInt32 nodeID; volatile UInt32 reset; volatile UInt32 packetControl; volatile UInt32 diagnosticStatus; volatile UInt32 phyControl; volatile UInt32 atRetries; volatile UInt32 ssnInterface; volatile UInt32 isochronousCycleTimer; volatile UInt32 reserved128[2]; PeleIsochControlRegisters itaControl; PeleIsochControlRegisters itbControl; PeleIsochControlRegisters iraControl; PeleIsochControlRegisters irbControl; volatile UInt32 rsuEnable; volatile UInt32 rsuInterrupt; volatile UInt32 rsuTablePtr; volatile UInt32 rsuInterruptSet; volatile UInt32 interruptEvents; volatile UInt32 interruptMask; volatile UInt32 interruptClear; volatile UInt32 interruptLevels; volatile UInt32 reserved190[4]; volatile UInt32 fifoFlags; volatile UInt32 fifoStatus; }; typedef struct PeleRegistersStruct PeleRegisters, *PeleRegistersPtr; // Bit definitions for Pele register contents and Pele-specific data formatting enum { kPeleBit0 = (1 << 0), kPeleBit1 = (1 << 1), kPeleBit2 = (1 << 2), kPeleBit3 = (1 << 3), kPeleBit4 = (1 << 4), kPeleBit5 = (1 << 5), kPeleBit6 = (1 << 6), kPeleBit7 = (1 << 7), kPeleBit8 = (1 << 8), kPeleBit9 = (1 << 9), kPeleBit10 = (1 << 10), kPeleBit11 = (1 << 11), kPeleBit12 = (1 << 12), kPeleBit13 = (1 << 13), kPeleBit14 = (1 << 14), kPeleBit15 = (1 << 15), kPeleBit16 = (1 << 16), kPeleBit17 = (1 << 17), kPeleBit18 = (1 << 18), kPeleBit19 = (1 << 19), kPeleBit20 = (1 << 20), kPeleBit21 = (1 << 21), kPeleBit22 = (1 << 22), kPeleBit23 = (1 << 23), kPeleBit24 = (1 << 24), kPeleBit25 = (1 << 25), kPeleBit26 = (1 << 26), kPeleBit27 = (1 << 27), kPeleBit28 = (1 << 28), kPeleBit29 = (1 << 29), kPeleBit30 = (1 << 30), kPeleBit31 = (1 << 31) }; #define PeleBitRange(start, end) \ ( \ ((((UInt32) 0xFFFFFFFF) << (31 - (end))) >> \ ((31 - (end)) + (start))) << \ (start) \ ) #define PeleBitRangePhase(start, end) \ (start) // Link Data Format defs. Although these are mostly 1394 constants, there can // be some FWIM-specific variations, so these are all included here. enum { kPeleDMA100mbps = 0, kPeleDMA200mbps = 1, kPeleDMA400mbps = 2 }; enum { // This is a value that Pele puts in the tCode position of the "header" // of the packet formed by concatenating all of the self ID packets. // This tCode isn't defined in 1394, but if it ever is, Pele won't // receive it, because the Link won't know how to process the CRC or // header. So we'll never get this "tCode", except for self-IDs. kPeleTCodeSelfID = 0x0E }; enum { kPelePacketPrio = PeleBitRange (0, 3), kPelePacketPrioPhase = PeleBitRangePhase (0, 3), kPelePacketTCode = PeleBitRange (4, 7), kPelePacketTCodePhase = PeleBitRangePhase (4, 7), kPelePacketSpd = PeleBitRange (16, 17), kPelePacketSpdPhase = PeleBitRangePhase (16, 17), kPelePacketEnableAT = kPeleBit19, kPelePacketAckSent = PeleBitRange (0, 3), kPelePacketAckSentPhase = PeleBitRangePhase (0, 3) }; enum { kPeleAsynchTLabel = PeleBitRange (10, 15), kPeleAsynchTLabelPhase = PeleBitRangePhase (10, 15), kPeleAsynchRt = PeleBitRange (8, 9), kPeleAsynchRtPhase = PeleBitRangePhase (8, 9), kPeleAsynchNew = 0, kPeleAsynchRetryA = 2, kPeleAsynchRetryB = 3, kPeleAsynchPriority = PeleBitRange (0, 3), kPeleAsynchPriorityPhase = PeleBitRangePhase (0, 3), kPeleAsynchDestinationID = PeleBitRange (16, 31), kPeleAsynchDestinationIDPhase = PeleBitRangePhase (16, 31), kPeleAsynchSourceID = PeleBitRange (16, 31), kPeleAsynchSourceIDPhase = PeleBitRangePhase (16, 31), kPeleAsynchDestinationOffsetHigh = PeleBitRange (0, 15), kPeleAsynchDestinationOffsetHighPhase = PeleBitRangePhase (0, 15), kPeleAsynchDestinationOffsetLow = PeleBitRange (0, 31), kPeleAsynchDestinationOffsetLowPhase = PeleBitRangePhase (0, 31), kPeleAsynchDataLength = PeleBitRange (16, 31), kPeleAsynchDataLengthPhase = PeleBitRangePhase (16, 31), kPeleAsynchExtendedTCode = PeleBitRange (0, 15), kPeleAsynchExtendedTCodePhase = PeleBitRangePhase (0, 15), kPeleAsynchAckSent = PeleBitRange (0, 3), kPeleAsynchAckSentPhase = PeleBitRangePhase (0, 3), kPeleAsynchRCode = PeleBitRange (12, 15), kPeleAsynchRCodePhase = PeleBitRangePhase (12, 15) }; //////////////////////////////////////////////////////////////////////////////// // // Pele register-specific constants. // // These apply to all of the DBDMA channels enum { kPeleSetRun = 0x80008000, kPeleClrRun = 0x80000000, kPeleSetPause = 0x40004000, kPeleClrPause = 0x40000000, kPeleSetFlush = 0x20002000, kPeleSetWake = 0x10001000, kPeleClrDead = 0x08000000, kPeleSetS7 = 0x00800080, kPeleClrS7 = 0x00800000, kPeleSetS6 = 0x00400040, kPeleClrS6 = 0x00400000, kPeleSetS5 = 0x00200020, kPeleClrS5 = 0x00200000, kPeleSetS4 = 0x00100010, kPeleClrS4 = 0x00100000, kPeleSetS3 = 0x00080008, kPeleClrS3 = 0x00080000, kPeleSetS2 = 0x00040004, kPeleClrS2 = 0x00040000, kPeleSetS1 = 0x00020002, kPeleClrS1 = 0x00020000, kPeleSetS0 = 0x00010001, kPeleClrS0 = 0x00010000, kPeleClrAll = 0xFFFF0000 }; enum { kPeleRun = 0x00008000, kPelePause = 0x00004000, kPeleFlush = 0x00002000, kPeleWake = 0x00001000, kPeleDead = 0x00000800, kPeleActive = 0x00000400, kPeleBt = 0x00000100, kPeleS7 = 0x00000080, kPeleS6 = 0x00000040, kPeleS5 = 0x00000020, kPeleS4 = 0x00000010, kPeleS3 = 0x00000008, kPeleS2 = 0x00000004, kPeleS1 = 0x00000002, kPeleS0 = 0x00000001 }; enum { kPeleOUTPUT_MORE = 0x00000000, kPeleOUTPUT_LAST = 0x10000000, kPeleINPUT_MORE = 0x20000000, kPeleINPUT_LAST = 0x30000000, kPeleSTORE_QUAD = 0x40000000, kPeleLOAD_QUAD = 0x50000000, kPeleNOP_CMD = 0x60000000, kPeleSTOP_CMD = 0x70000000, kPeleCmdMask = 0xF0000000 }; enum { kPeleKEY_STREAM0 = 0x00000000, kPeleKEY_STREAM1 = 0x01000000, kPeleKEY_STREAM2 = 0x02000000, kPeleKEY_STREAM3 = 0x03000000, kPeleKEY_REGS = 0x05000000, kPeleKEY_SYSTEM = 0x06000000, kPeleKEY_DEVICE = 0x07000000, kPeleKeyMask = 0x07000000, kPeleIntNever = 0x00000000, kPeleIntIfTrue = 0x00100000, kPeleIntIfFalse = 0x00200000, kPeleIntAlways = 0x00300000, kPeleIMask = 0x00300000, kPeleBranchNever = 0x00000000, kPeleBranchIfTrue = 0x00040000, kPeleBranchIfFalse = 0x00080000, kPeleBranchAlways = 0x000C0000, kPeleBMask = 0x000C0000, kPeleWaitNever = 0x00000000, kPeleWaitIfTrue = 0x00010000, kPeleWaitIfFalse = 0x00020000, kPeleWaitAlways = 0x00030000, kPeleWMask = 0x00030000, kPeleCommandMask = 0xFFFF0000, kPeleReqCountMask = 0x0000FFFF }; enum { kPeleXferStatusRun = kPeleRun << 16, kPeleXferStatusPause = kPelePause << 16, kPeleXferStatusFlush = kPeleFlush << 16, kPeleXferStatusWake = kPeleWake << 16, kPeleXferStatusDead = kPeleDead << 16, kPeleXferStatusActive = kPeleActive << 16, kPeleXferStatusBt = kPeleBt << 16, kPeleXferStatusS7 = kPeleS7 << 16, kPeleXferStatusS6 = kPeleS6 << 16, kPeleXferStatusS5 = kPeleS5 << 16, kPeleXferStatusS4 = kPeleS4 << 16, kPeleXferStatusS3 = kPeleS3 << 16, kPeleXferStatusS2 = kPeleS2 << 16, kPeleXferStatusS1 = kPeleS1 << 16, kPeleXferStatusS0 = kPeleS0 << 16, kPeleXferStatusMask = 0xFFFF0000, kPeleResCountMask = 0x0000FFFF }; // Version register [version, 100] enum { kPeleVersionVersion = PeleBitRange(16, 31), kPeleVersionVersionPhase = PeleBitRangePhase(16, 31), kPeleVersionRevision = PeleBitRange(0, 15), kPeleVersionRevisionPhase = PeleBitRangePhase(0, 15) }; // Control register [control, 104] enum { kPeleControlByteSwap = kPeleBit31, // Formerly "littleEndian" kPeleControlPhysDMAEnable = PeleBitRange(24, 25), kPeleControlPhysDMAEnablePhase = PeleBitRangePhase(24, 25), kPeleControlCycleSource = kPeleBit18, kPeleControlCycleMaster = kPeleBit17, kPeleControlCycleTimerEnable = kPeleBit16, kPeleControlStrictIsoch = kPeleBit8, kPeleControlReceiveEnable = kPeleBit1, kPeleControlTransmitEnable = kPeleBit0, kPelePhysDMAnoAccess = 0, kPelePhysDMAreadOnly = 1, kPelePhysDMAreadWrite = 2 }; // Node Identification register [nodeID, 108] enum { kPeleNodeIDValid = kPeleBit31, kPeleNodeIDRoot = kPeleBit23, kPeleNodeIDFullID = PeleBitRange(0, 15), kPeleNodeIDFullIDPhase = PeleBitRangePhase(0, 15), kPeleNodeIDBusNumber = PeleBitRange(6, 15), kPeleNodeIDBusNumberPhase = PeleBitRangePhase(6, 15), kPeleNodeIDNodeNumber = PeleBitRange(0, 5), kPeleNodeIDNodeNumberPhase = PeleBitRangePhase(0, 5) }; // Reset register [reset, 10C] enum { kPeleResetLinkOnEnable = kPeleBit8, kPeleResetReceiver = kPeleBit5, kPeleResetTransmitter = kPeleBit4, kPeleResetRF = kPeleBit2, kPeleResetITF = kPeleBit1, kPeleResetATF = kPeleBit0 }; // Packet Control register [packetControl, 110] enum { kPelePacketControlPSBusyClr = kPeleBit17, kPelePacketControlPSBusy = kPeleBit16, kPelePacketControlBsyCtrl = PeleBitRange(8, 10), kPelePacketControlBsyCtrlPhase = PeleBitRangePhase(8, 10), kPelePacketControlRcvSelfID = kPeleBit5, kPelePacketControlEnableSnoop = kPeleBit4, kPeleBsyCtrlDualPhase = 0, kPeleBsyCtrlSendBusyA = 1, kPeleBsyCtrlSendBusyB = 2, kPeleBsyCtrlSendBusyX = 3, kPeleBsyCtrlAlwaysSendBusyDual = 4, kPeleBsyCtrlAlwaysSendBusyA = 5, kPeleBsyCtrlAlwaysSendBusyB = 6, kPeleBsyCtrlAlwaysSendBusyX = 7 }; // Diagnostic Status register [diagnosticStatus, 114] enum { kPeleDiagIsoActive = kPeleBit4, kPeleDiagBusyState = kPeleBit2, kPeleDiagSubactionGap = kPeleBit1, kPeleDiagArbResetGap = kPeleBit0 }; // Phy Control register [phyControl, 118] enum { kPelePhyControlRdDone = kPeleBit31, kPelePhyControlRdAddr = PeleBitRange(24, 27), kPelePhyControlRdAddrPhase = PeleBitRangePhase(24, 27), kPelePhyControlRdData = PeleBitRange(16, 23), kPelePhyControlRdDataPhase = PeleBitRangePhase(16, 23), kPelePhyControlRdReg = kPeleBit15, kPelePhyControlWrReg = kPeleBit14, kPelePhyControlWrAddr = PeleBitRange(8, 11), kPelePhyControlWrAddrPhase = PeleBitRangePhase(8, 11), kPelePhyControlWrData = PeleBitRange(0, 7), kPelePhyControlWrDataPhase = PeleBitRangePhase(0, 7) }; // ATRetries register [atRetries, 11C] enum { kPeleATRetriesPSRetryCnt = PeleBitRange(16, 19), kPeleATRetriesPSRetryCntPhase = PeleBitRangePhase(16, 19), kPeleATRetriesAsyncRetryCnt = PeleBitRange(8, 11), kPeleATRetriesAsyncRetryCntPhase = PeleBitRangePhase(8, 11), kPeleATRetriesMaxRetries = PeleBitRange(0, 3), kPeleATRetriesMaxRetriesPhase = PeleBitRangePhase(0, 3) }; // SSN Interface register [ssnInterface, 120] // Warning, some parts may do this backwards (low=1, tristate=0). enum { kPeleSSNSerialDtIn = kPeleBit1, kPeleSSNSerialDtOut = kPeleBit0, kPeleSSNOutLow = 0, kPeleSSNOutTristate = kPeleBit0 }; // Isochronous Cycle Timer register [isochronousCycleTimer, 124] enum { kPeleICTSeconds = PeleBitRange(25, 31), kPeleICTSecondsPhase = PeleBitRangePhase(25, 31), kPeleICTCount = PeleBitRange(12, 24), kPeleICTCountPhase = PeleBitRangePhase(12, 24), kPeleICTOffset = PeleBitRange(0, 11), kPeleICTOffsetPhase = PeleBitRangePhase(0, 11) }; // Isochronous Event Cycle registers // [itaControl.eventCycle, 130] // [itbControl.eventCycle, 140] // [iraControl.eventCycle, 150] // [irbControl.eventCycle, 160] enum { kPeleIsochEventCycle = PeleBitRange(12, 31), kPeleIsochEventCyclePhase = PeleBitRangePhase(12, 31) }; // IT DMA Configuration registers // [itaControl.configuration, 134] // [itbControl.configuration, 144] enum { kPeleITDMAconfigTag = PeleBitRange(30, 31), kPeleITDMAconfigTagPhase = PeleBitRangePhase(30, 31), kPeleITDMAconfigChannel = PeleBitRange(24, 29), kPeleITDMAconfigChannelPhase = PeleBitRangePhase(24, 29), kPeleITDMAconfigSpeed = PeleBitRange(16, 17), kPeleITDMAconfigSpeedPhase = PeleBitRangePhase(16, 17), kPeleITDMAconfigSync = PeleBitRange(12, 15), kPeleITDMAconfigSyncPhase = PeleBitRangePhase(12, 15), kPeleITDMAconfigRateMode = kPeleBit8, kPeleITDMAconfigStartOnEvent = PeleBitRange(4, 5), kPeleITDMAconfigStartOnEventPhase = PeleBitRangePhase(4, 5), kPeleITDMAconfigStopOnEvent = PeleBitRange(0, 1), kPeleITDMAconfigStopOnEventPhase = PeleBitRangePhase(0, 1) // See IR DMA for Start/Stop Event codes }; // IT DMA Bandwidth Control resigster (AKA I+N/D) // [itaControl.bandwidthControl, 138] // [itbControl.bandwidthControl, 148] enum { kPeleITDMABandwidthI = PeleBitRange(16, 27), kPeleITDMABandwidthIPhase = PeleBitRangePhase(16, 27), kPeleITDMABandwidthN = PeleBitRange(8, 15), kPeleITDMABandwidthNPhase = PeleBitRangePhase(8, 15), kPeleITDMABandwidthD = PeleBitRange(0, 7), kPeleITDMABandwidthDPhase = PeleBitRangePhase(0, 7) }; // IR DMA Configuration registers // [iraControl.configuration, 154] // [irbControl.configuration, 164] enum { kPeleIRDMAconfigTag = PeleBitRange(30, 31), kPeleIRDMAconfigTagPhase = PeleBitRangePhase(30, 31), kPeleIRDMAconfigChannel = PeleBitRange(24, 29), kPeleIRDMAconfigChannelPhase = PeleBitRangePhase(24, 29), kPeleIRDMAconfigSync = PeleBitRange(12, 15), kPeleIRDMAconfigSyncPhase = PeleBitRangePhase(12, 15), kPeleIRDMAconfigBufferMode = kPeleBit8, kPeleIRDMAconfigStartOnEvent = PeleBitRange(4, 5), kPeleIRDMAconfigStartOnEventPhase = PeleBitRangePhase(4, 5), kPeleIRDMAconfigStopOnEvent = PeleBitRange(0, 1), kPeleIRDMAconfigStopOnEventPhase = PeleBitRangePhase(0, 1), kPeleEventChannelProgram = 0, kPeleEventCycleNumber = 1, kPeleEventSync = 2, kPeleEventOccured = 3 }; // Read Response registers // [rsuEnable, 170] // [rsuInterrupt, 174] // [rsuTablePtr, 178] // [rsuInterruptSet, 17C] // There's nothing to enum for these // Interrupt Events, Mask, Level, and Clear registers // [interruptEvents, 180] // [interruptMask, 184] // [interruptClear, 188] // [interruptLevels, 18C] enum { kPeleIntITBadFormat = kPeleBit31, // Spec lists these in kPeleIntPhyRegRcvd = kPeleBit30, // reverse order, unlike kPeleIntCycleTooLong = kPeleBit29, // all other registers. kPeleIntPSOutOfRetries = kPeleBit28, kPeleIntRSDone = kPeleBit27, // Here they are listed kPeleIntRSXferErr = kPeleBit26, // in "natural" order, ie, kPeleIntPWQUxferErr = kPeleBit25, // left-to-right. kPeleIntPRQUxferErr = kPeleBit24, kPeleIntTCodeErr = kPeleBit23, kPeleIntHdrErr = kPeleBit22, kPeleIntSentRej = kPeleBit21, kPeleIntATBadFormat = kPeleBit20, kPeleIntCycleLost = kPeleBit19, kPeleIntCycleSeconds = kPeleBit18, kPeleIntCycleStart = kPeleBit17, kPeleIntTxRdy = kPeleBit16, kPeleIntRcvData = kPeleBit15, kPeleIntPhyInt = kPeleBit14, kPeleIntCmdReset = kPeleBit13, kPeleIntBusReset = kPeleBit12, kPeleIntCycleEventIRB = kPeleBit11, kPeleIntCycleEventIRA = kPeleBit10, kPeleIntCycleEventITB = kPeleBit9, kPeleIntCycleEventITA = kPeleBit8, kPeleIntDMAIRB = kPeleBit5, kPeleIntDMAIRA = kPeleBit4, kPeleIntDMAITB = kPeleBit3, kPeleIntDMAITA = kPeleBit2, kPeleIntDMAAR = kPeleBit1, kPeleIntDMAAT = kPeleBit0 }; // FIFO Flags Register [fifoFlags, 1A0] // Warning, may not exist in some Pele parts enum { kPeleFifoRcvFull = kPeleBit18, kPeleFifoRcvAlFull = kPeleBit17, kPeleFifoRcvEmpty = kPeleBit16, kPeleFifoIsochTxFull = kPeleBit10, kPeleFifoIsochTxAlFull = kPeleBit9, kPeleFifoIsochTxEmpty = kPeleBit8, kPeleFifoAsynchTxFull = kPeleBit2, kPeleFifoAsynchTxAlFull = kPeleBit1, kPeleFifoAsynchTxEmpty = kPeleBit0 }; // FIFO Status Register [fifoStatus, 1A4] // Warning, may not exist in some Pele parts enum { kPeleFifoRcvPtr = PeleBitRange(24, 30), kPeleFifoRcvPtrPhase = PeleBitRangePhase(24, 30), kPeleFifoIsochTxPtr = PeleBitRange(16, 22), kPeleFifoIsochTxPtrPhase = PeleBitRangePhase(16, 22), kPeleFifoAsynchTxPtr = PeleBitRange(8, 14), kPeleFifoAsynchTxPtrPhase = PeleBitRangePhase(8, 14), kPeleFifoRcvWatermark = kPeleBit2, kPeleFifoIsochTxWatermark = kPeleBit1, kPeleFifoAsynchTxWatermark = kPeleBit0 }; // Defs for pending FWIM commands. enum { kPelePendingFWIMCommandBusy = 1 }; // Various private data structures used within PeleFWIM. struct PeleIsochPortDataStruct { DCLProgramID dclProgramID, // ID of DCL program we're using. originalDCLProgramID, // Original DCL program ID. translatedDCLProgramID; // Translated DCL program ID. UInt32 channelNum; // Isoch channel number used for this port. UInt32 speed; // Speed of this port. Boolean talking; // True if port is for talking. }; typedef struct PeleIsochPortDataStruct PeleIsochPortData, *PeleIsochPortDataPtr; // There is one of these structs for each asynch receive buffer/descriptor pair. // It holds auxillary data, like the asynch processing paramaters. struct PeleAsynchRxDMADataStruct { struct PeleAsynchRxDMADataStruct *pNextRxDMAData; // Pointer to next DMA data. struct PeleFWIMDataStruct *pPeleFWIMData; // Pointer to Pele FWIM data. PeleDMAPtr pDMA; // Logical pointer to descriptor Ptr pDMAPhysical; // Physical pointer to descriptor. Ptr packetBuffer; // Logical packet buffer of DMA. FWIMProcessAsynchParams fwimProcessAsynchParams;// Params for processing received requests. }; typedef struct PeleAsynchRxDMADataStruct PeleAsynchRxDMAData, *PeleAsynchRxDMADataPtr; struct PeleAsynchTxDMADataStruct { struct PeleAsynchTxDMADataStruct *pNextTxDMAData;// Pointer to next descriptor. struct PeleFWIMDataStruct *pPeleFWIMData; // Pointer to Pele FWIM data. PeleDMAPtr pDMA; // Logical pointer to descriptor Ptr pDMAPhysical; // Physical pointer to descriptor. }; typedef struct PeleAsynchTxDMADataStruct PeleAsynchTxDMAData, *PeleAsynchTxDMADataPtr; // Private data structure for PeleFWIM - one per Pele struct PeleFWIMDataStruct { // Some fields within this struct will be physically addressed by commands in a PCL program. // We will only map the first page of this struct physically, so these fields must be within // the first page. So don't rearrange this part of the struct. DCLCommandPtr pDCLInterruptTail[kNumDMAChannels]; // Tails of DCL interrupt queues. volatile UInt32 asynchTxDoneFlag; // Flag indicating that asynchronous transmit has finished. UInt32 asynchRxOverflowFlag; // Flag indicating an overflow in asynch receive. // Nothing below this line will be accessed via physical addresses PhysicalAddress fwimDataPhys; // Physical address of this struct IOPreparationTable fwimDataIOPrep; // ioPrep data for this struct FWIMID fwimID; // ID for this FWIM RegEntryID FWIMRegEntryID; // Name registry ID for TI card. UInt32 generation; // Current bus generation number. Boolean generationValid; // Generation number is valid. // Could probably remove this Boolean root; // True if we're root. TimerID resetDebounceTimerID; // TimerID for debouncing resets Boolean resetDebounceTimerSet; // Flag indicating the above timer is running TimerID requestTimeoutTimerID; // TimerID to indicate timeout of a read/write request Boolean requestTimeoutTimerSet; // Flag indicating the above timer is running FWDeferredTaskID busResetDeferredTaskID; // Deferred task ID for handling bus resets. Boolean busResetDTScheduled; // True if we've scheduled a DT to handle bus resets. FWDeferredTaskID asynchReceiveDeferredTaskID; // Deferred task ID for handling received asynch packets. Boolean asynchReceiveDTScheduled; // True if we've sceduled a DT to handle received asynch packets. FWDeferredTaskID isochReceiveDeferredTaskID; // Deferred task ID for handling received isoch packets. Boolean isochReceiveDTScheduled; // True if we've sceduled a DT to handle received isoch packets. FWDeferredTaskID isochTransmitDeferredTaskID; // Deferred task ID for handling transmitted isoch packets. Boolean isochTransmitDTScheduled; // True if we've sceduled a DT to handle transmitted isoch packets. FWDeferredTaskID miscInterruptDeferredTaskID; // Deferred task ID for handling misc interrupts. Boolean miscInterruptDTScheduled; // True if we've sceduled a DT to handle misc interrupts. UInt32 miscInterrupt; // Miscellaneous interrupt to deal with FWIMCommandParamsPtr pPendingFWIMCommand; // Pending FWIM command. OSStatus pendingFWIMCommandStatus; // Internal status of pending FWIM command. FWIMCommandParamsPtr pPendingFWIMResponseCommand; // Pending FWIM response command. UInt32 transactionLabel; // Label used for current transaction UInt32 tCode; // TCode for current transaction. // Is this used? DCLCommandPtr pCurrentDCLCommand; // Pointer to current DCL command. InterruptSetMember interruptSetMember; void *oldInterruptRefCon; InterruptHandler oldInterruptHandler; InterruptEnabler interruptEnabler; InterruptDisabler interruptDisabler; PeleRegistersPtr pPeleRegisters; // Register file Ptr asynchBuf[kAsynchRxBufs]; // Non-isoch Ptr asynchBufPhys[kAsynchRxBufs]; // Physical addrs PeleDMA *asynchXmitDMA; // two for transmit Ptr asynchXmitDMAPhys; // Physical addrs PeleAsynchTxDMADataPtr pNextAsynchTxDMAData; // Pointer to next active asynch transmit PCL to process. PeleAsynchTxDMADataPtr pLastAsynchTxDMAData; // Pointer to last active asynch transmit PCL. PeleAsynchTxDMADataPtr asynchTxDoneDMASegment; // PCL segment to deal with finished asynch transmit. PeleAsynchTxDMADataPtr AsynchTxDMADataList; // List of data records for asynch transmit PCLs. PeleDMA *asynchDMA; // asynch DMA loop /zzz rename PeleAsynchRxDMADataPtr pNextAsynchRxDMAData; // Next asynch receive DMA to process. PeleAsynchRxDMADataPtr pLastAsynchRxDMAData; // Last available asynch receive DMA. PeleAsynchRxDMADataPtr pStartAsynchRxDMAData; // Asynch receive PCL to start receive program. UInt32 numAsynchRxDMAsPrimed; // Number of receive PCLs primed. PeleAsynchRxDMADataPtr asynchRxOverflowDMASegment; // DMA segment to deal with asynch receive overflow. Ptr asynchDMAPhys; // Physical addrs PeleAsynchRxDMADataPtr asynchRxDMADataList; // List of data records for asynch receive PCLs. Ptr asynchXmitBuf; // For Asynch xmit Ptr asynchXmitBufPhys; // Physical IOPreparationTable ioPrep; // For VM PhysicalAddress physAddrs[kAsynchRxBufs+20]; // Page table - fix this //rename PeleIsochPortDataPtr lynxIsochPortDataList[kNumDMAChannels]; // List of isoch port data records. UInt32 pageSize, // Physical page size and shift for VM. pageShift; //unused? UInt32 bitBucket; // Bit bucket to dump stuff into. TimerID delayedResetTimerID; // (temporary hack) Boolean delayedResetTimerSet; // Flag indicating the above timer is running UInt8 lastPhyReg0; // Last known value of PHY register zero UInt32 lastPhyControl; // Last known value of PHY control register }; typedef struct PeleFWIMDataStruct PeleFWIMData, *PeleFWIMDataPtr; // The DBDMA Pool is actually an allocate-once memory source for descriptors. // We allocate one large block and then break it up into DBDMA descriptors. // We can allocate more large blocks if required. Blocks are released when // a DBDMA program is no longer needed. enum { kDMAPoolSize = 480, kDMAAlignmentMask = 0xFFFFFFF0 }; typedef struct PeleDMAPoolDataStruct PeleDMAPoolData, *PeleDMAPoolDataPtr; struct PeleDMAPoolDataStruct { PeleDMAPoolDataPtr pNextPeleDMAPoolData; // Link to next PCL pool data record. UInt32 nextFreeDMA; // Next free PCL in pool. PeleDMAPtr alignedDMAPoolBase; // 128-byte-aligned PCL pool base address. UInt32 alignedDMAPoolBasePhys; // Physical addr of same LogicalAddress poolAllocatedAddress; // Actual allocated address IOPreparationTable ioPrep; // For VM PhysicalAddress physAddrs[20]; // warning, arbitrary constant PeleDMA dmaPoolDummy[kDMAPoolSize]; // Space for PCL pool array. }; // We create one of these for each DCL to hold compiler private information: struct PeleDCLCompilerDCLDataStruct { PeleDMAPtr pDMA; // pointer to (first) descriptor PhysicalAddress pDMAPhys; // Physical address of same }; typedef struct PeleDCLCompilerDCLDataStruct PeleDCLCompilerDCLData, *PeleDCLCompilerDCLDataPtr; // As we compile DCLs into DBDMA, this structure keeps track of general // information. There is one of these for each program being compiled. struct PeleDCLCompilerEngineDataStruct { PeleFWIMDataPtr pPeleFWIMData; // Our FWIM data. PeleDMAPtr pStartDMA; // Pointer to first DBDMA in compiled program. PeleDMAPoolDataPtr pPeleDMAPoolDataList; // List of DBDMA pools allocated for this copmiled program. UInt32 engineGeneration; // For faster lookups IOPreparationTable ioPrep; // For all buffers/etc PhysicalAddress *physAddrs; // Page table (of sorts) PeleDCLCompilerDCLDataPtr pPeleDCLCompilerDCLData;// Base of compiler data list }; typedef struct PeleDCLCompilerEngineDataStruct PeleDCLCompilerEngineData, *PeleDCLCompilerEngineDataPtr; // As we compile DCLs into DBDMA, this structure keeps track of DBDMA-oriented // information. There is one of these for each program being compiled. struct PeleDMABuildStateStruct { PeleFWIMDataPtr pPeleFWIMData; // Our FWIM data. PeleDCLCompilerEngineDataPtr pPeleDCLCompilerEngineData; UInt32 dmaChannelNum; // DMA channel number we're building for. PeleDMAPoolDataPtr pPeleDMAPoolDataList; // List of DBDMA pools allocated for this build. UInt32 isochChannelNum; // Isochronous channel number. UInt32 *pLastBranch; // unfilled branch from last DBDMA }; typedef struct PeleDMABuildStateStruct PeleDMABuildState, *PeleDMABuildStatePtr; #if PRAGMA_ALIGN_SUPPORTED #pragma options align=reset #endif #if PRAGMA_IMPORT_SUPPORTED #pragma import off #endif #ifdef __cplusplus } #endif #endif /* __PELEFWIM__ */